At submicron manufacturing technology nodes, pro- cess variations affectcircuit performance significantly. To counter these variations, engineers arereserving more timing margin to maintain yield, leading to an unaffordableoverdesign. Most of these margins, however, are wasted after manufacturing,because process variations cause only some chips to be really slow, while otherchips can easily meet given timing specifications. To reduce this pessimism, wecan reserve less timing margin and tune failed chips after manufacturing withclock buffers to make them meet timing specifications. With this post-siliconclock tuning, critical paths can be balanced with neighboring paths in eachchip specifically to counter the effect of process variations. Consequently,chips with timing failures can be rescued and the yield can thus be improved.This is specially useful in high- performance designs, e.g., high-end CPUs,where clock binning makes chips with higher performance much more profitable.In this paper, we propose a method to determine where to insert post-silicontuning buffers during the design phase to improve the overall profit with clockbinning. This method learns the buffer locations with a Sobol sequenceiteratively and reduces the buffer ranges afterwards with tuning concentrationand buffer grouping. Experimental results demonstrate that the proposed methodcan achieve a profit improvement of about 14% on average and up to 26%, withonly a small number of tuning buffers inserted into the circuit.
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